1. Field of the Invention
This invention relates to computer systems, and more particularly, to a method and apparatus for providing flow control of input/output operations of first-in first out (FIFO) circuits in computer systems.
2. History of the Prior Art
Modern computer system are typically based on an architecture which was first offered in the Digital Equipment Corporation (DEC) PDP 11 computer. One problem with this architecture as with earlier IBM and CDC mainframe architectures is that writing directly to the input/output devices of the system by an application program is prohibited. Although this architecture allows all of the facilities of the central processing unit to be used for input/output, it requires that the operating system running on the central processing unit attend to all of the input/output functions using trusted code. This significantly slows any input/output operation of the computer.
In contrast to earlier mainframe systems, in the PDP-11 architecture, there is no process by which the input/output performance of the system can be increased except by increasing the speed of the central processing unit or the input/output bus. This is an especial problem for programs which make heavy use of input output/devices such as video and game programs which manipulate graphics and high quality sound extensively.
In a modern computer, the central processing unit and the input/output devices operate at different speeds. It can be very inefficient for a modern central processing unit to wait until an input/output write operation is complete before performing the next operation which often has nothing to do with input/output. On the other hand, a central processing unit has to wait for the result of a read operation because it needs the result produced.
Since most central processing unit accesses to input/output devices are write operations, the designers of systems and input/output devices attempt to decouple the central processing unit and input/output devices as far as write operations are concerned by implementing write queues using first-in first-out (FIFO) write buffers. These buffers may appear at various places in a particular implementation: as a part of the central processing unit, as part of a bridge chip, or as part of an input/output device.
One problem raised in systems using FIFO buffers is that an input/output device and the buffers supplying it must accept all information written to them over the input/output bus. Although some input/output buses allow devices to "hold off" writes, that is, delay the completion of the write operation until the device has enough resources available to store the data, there is always a limit to how long a write can be held off. If a write is held off too long the data will be lost. In the limit, the input/output device has no alternative but to store all data written to it. In a system utilizing FIFO buffers for storage of this data at the input/output device, the FIFO buffers must ultimately store the data.
Since any practical input/output device will have limited FIFO buffer storage for holding data written to it over the input/output bus, any architecture for input/output devices must include some technique for controlling the flow of data so that this storage is not exhausted.
A new input/output architecture which allows input/output operations to proceed at a faster rate by allowing application programs to write directly to input/output devices used with advanced multi-tasking operating systems has been designed. One of the features of this system is the use of a write buffering arrangement including FIFO buffers.
In order to utilize FIFO buffers, it is necessary to provide arrangements by which commands directed to input/output devices from different application programs may utilize the FIFO buffers safely while writing directly to the input/output devices. The new architecture including such a FIFO input buffer is described in U.S. Pat. No. 5,696,990, entitled Method and Apparatus for Providing Improved Flow Control For Input/Output Operations a Computer System Having a FIFO Circuit And An Overflow Storage Area, issued Dec. 9, 1997, to Rosenthal et al.
In the new input/output architecture, it was contemplated that an application program executing on a central processor would write commands directly to the FIFO buffers. Because of the limited size of such buffers, the variable amounts of data to be transferred, and the need for the central processor to read a register associated with the FIFO buffers in order to know whether additional commands could be written to the buffers, the process of having the central processor write directly to the FIFO and the associated I/O devices is not always fast enough. It is desirable to provide circuitry and a method for accomplishing faster writes of data directly from an application program to I/O devices.